Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8916437 | Insulated gate field effect transistor having passivated schottky barriers to the channel | Daniel J. Connelly | 2014-12-23 |
| 8766336 | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions | Daniel J. Connelly | 2014-07-01 |
| 8658523 | Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s) | Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton | 2014-02-25 |
| 8431469 | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions | Daniel J. Connelly | 2013-04-30 |
| 8377767 | Insulated gate field effect transistor having passivated schottky barriers to the channel | Daniel J. Connelly | 2013-02-19 |
| 8263467 | Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor | Daniel J. Connelly, Paul A. Clifton, Carl M. Faulkner | 2012-09-11 |
| 7902029 | Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor | Daniel J. Connelly, Paul A. Clifton, Carl M. Faulkner | 2011-03-08 |
| 7883980 | Insulated gate field effect transistor having passivated schottky barriers to the channel | Daniel J. Connelly | 2011-02-08 |
| 7884003 | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions | Daniel J. Connelly | 2011-02-08 |
| 7816240 | Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s) | Carl M. Faulkner, Daniel J. Connelly, Paul A. Clifton | 2010-10-19 |
| 7615402 | Electrostatically operated tunneling transistor | — | 2009-11-10 |
| 7462860 | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions | Daniel J. Connelly | 2008-12-09 |
| 7382021 | Insulated gate field-effect transistor having III-VI source/drain layer(s) | Carl M. Faulkner, Daniel J. Connelly | 2008-06-03 |
| 7176483 | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions | Daniel J. Connelly | 2007-02-13 |
| 7112478 | Insulated gate field effect transistor having passivated Schottky barriers to the channel | Daniel J. Connelly | 2006-09-26 |
| 7084423 | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions | Daniel J. Connelly | 2006-08-01 |
| 6891234 | Transistor with workfunction-induced charge layer | Daniel J. Connelly, Carl M. Faulkner | 2005-05-10 |
| 6833556 | Insulated gate field effect transistor having passivated schottky barriers to the channel | Daniel J. Connelly | 2004-12-21 |
| 6261943 | Method for fabricating free-standing thin metal films | — | 2001-07-17 |
| 6236033 | Enhanced optical transmission apparatus utilizing metal films having apertures and periodic surface topography | Thomas Ebbesen, Tineke Thio, Henri J. Lezec | 2001-05-22 |
| 6198113 | Electrostatically operated tunneling transistor | — | 2001-03-06 |
| 5586064 | Active magnetic field compensation system using a single filter | — | 1996-12-17 |