Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8658523 | Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s) | Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp | 2014-02-25 |
| 8263467 | Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor | Daniel E. Grupp, Daniel J. Connelly, Paul A. Clifton | 2012-09-11 |
| 7902029 | Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor | Daniel E. Grupp, Daniel J. Connelly, Paul A. Clifton | 2011-03-08 |
| 7816240 | Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s) | Daniel J. Connelly, Paul A. Clifton, Daniel E. Grupp | 2010-10-19 |
| 7382021 | Insulated gate field-effect transistor having III-VI source/drain layer(s) | Daniel J. Connelly, Daniel E. Grupp | 2008-06-03 |
| 6891234 | Transistor with workfunction-induced charge layer | Daniel J. Connelly, Daniel E. Grupp | 2005-05-10 |