Issued Patents 2025
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426226 | Macro and SRAM bit cell cooptimizatoin for performance (long/shortwordline combo SRAM) | Ping-Wei Wang, Kuo-Hsiu Hsu, Kian-Long Lim, Yu-Kuan Lin, Chia-Hao Pao +3 more | 2025-09-23 |
| 12374590 | Test structure and test method thereof | Jing-Yi Lin, Chih-Chuan Yang, Kuo-Hsiu Hsu | 2025-07-29 |
| 12367925 | Static random access memory layout | Chih-Chuan Yang, Jui Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu +1 more | 2025-07-22 |
| 12363893 | Semiconductor memory structure | Hsin-Wen Su, Shih-Hao Lin, Yu-Kuan Lin, Ping-Wei Wang | 2025-07-15 |
| 12349330 | Shared pick-up regions for memory devices | Chih-Chuan Yang, Chao-Yuan Chang, Shih-Hao Lin, Chia-Hao Pao, Feng-Ming Chang +1 more | 2025-07-01 |
| 12349329 | Memory device and method for forming the same | Hsin-Wen Su, Chih-Chuan Yang, Shih-Hao Lin, Yu-Kuan Lin, Ping-Wei Wang | 2025-07-01 |
| 12336281 | Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof | Chia-Hao Pao, Chih-Hsuan Chen, Shih-Hao Lin | 2025-06-17 |
| 12302609 | Semiconductor device including alternating semiconductor layers with different widths and method for forming the same | Hsin-Wen Su, Yu-Kuan Lin, Shih-Hao Lin, Ping-Wei Wang | 2025-05-13 |
| 12219747 | Memory active region layout for improving memory performance | Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Chih-Hsuan Chen, Kian-Long Lim +3 more | 2025-02-04 |
| 12200921 | Memory device and method for forming the same | Hsin-Wen Su, Chih-Chuan Yang, Shih-Hao Lin, Yu-Kuan Lin, Ping-Wei Wang | 2025-01-14 |