Issued Patents 2025
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12356660 | Multi-gate device and related methods | Shih-Hao Lin, Chih-Chuan Yang, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su +1 more | 2025-07-08 |
| 12336281 | Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof | Chia-Hao Pao, Lien Jung Hung, Shih-Hao Lin | 2025-06-17 |
| 12315738 | Method of forming a gate structure including semiconductor material implantation into dummy gate stack | Shih-Hao Lin, Jui-Lin Chen, Hsin-Wen Su, Kian-Long Lim, Bwo-Ning Chen | 2025-05-27 |
| 12294030 | Nano-sheet-based complementary metal-oxide-semiconductor devices with asymmetric inner spacers | Shih-Hao Lin, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su +1 more | 2025-05-06 |
| 12249636 | Tuning gate lengths in multi-gate field effect transistors | Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Ping-Wei Wang | 2025-03-11 |
| 12250803 | Device and method for tuning threshold voltage | Chia-Hao Pao, Shih-Hao Lin | 2025-03-11 |
| 12219747 | Memory active region layout for improving memory performance | Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Kian-Long Lim, Chao-Yuan Chang +3 more | 2025-02-04 |
| 12218227 | Semiconductor structure | Shih-Hao Lin, Chia-Hung Chou, Ping-En CHENG, Hsin-Wen Su, Chien-Chih Lin +1 more | 2025-02-04 |