Issued Patents 2025
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406705 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Harsh Rawat, Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI | 2025-09-02 |
| 12386506 | Tagged memory operated at lower VMIN in error tolerant system | Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Singh, Manuj AYODHYAWASI | 2025-08-12 |
| 12361982 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Harsh Rawat, Promod Kumar, Kedar Janardan Dhori, Manuj AYODHYAWASI | 2025-07-15 |
| 12353341 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Bhupender Singh, Hitesh Chawla, Tanuj KUMAR, Harsh Rawat, Kedar Janardan Dhori +2 more | 2025-07-08 |
| 12354644 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Promod Kumar, Manuj AYODHYAWASI, Harsh Rawat | 2025-07-08 |
| 12292780 | Computing system power management device, system and method | Anuj Grover, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar | 2025-05-06 |
| 12243584 | In-memory compute array with integrated bias elements | Anuj Grover, Tanmoy Roy | 2025-03-04 |
| 12237007 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Kedar Janardan Dhori, Harsh Rawat, Promod Kumar, Manuj AYODHYAWASI | 2025-02-25 |