Issued Patents 2025
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12406705 | In-memory computation circuit using static random access memory (SRAM) array segmentation | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2025-09-02 |
| 12400707 | Device and method for reading data from memory cells | — | 2025-08-26 |
| 12361982 | Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode | Harsh Rawat, Nitin Chawla, Promod Kumar, Manuj AYODHYAWASI | 2025-07-15 |
| 12353341 | Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selection | Bhupender Singh, Hitesh Chawla, Tanuj KUMAR, Harsh Rawat, Promod Kumar +2 more | 2025-07-08 |
| 12354644 | Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Nitin Chawla, Promod Kumar, Manuj AYODHYAWASI, Harsh Rawat | 2025-07-08 |
| 12328858 | Silicon-on-insulator semiconductor device with a static random access memory circuit | Olivier Weber, Promod Kumar, Shafquat Jahan Ahmed, Christophe Lecocq, Pascal Urard | 2025-06-10 |
| 12292780 | Computing system power management device, system and method | Nitin Chawla, Anuj Grover, Giuseppe Desoli, Thomas Boesch, Promod Kumar | 2025-05-06 |
| 12237007 | Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) | Harsh Rawat, Promod Kumar, Nitin Chawla, Manuj AYODHYAWASI | 2025-02-25 |