Issued Patents 2025
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386506 | Tagged memory operated at lower VMIN in error tolerant system | Nitin Chawla, Giuseppe Desoli, Thomas Boesch, Surinder Singh, Manuj AYODHYAWASI | 2025-08-12 |
| 12292780 | Computing system power management device, system and method | Nitin Chawla, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar | 2025-05-06 |
| 12243584 | In-memory compute array with integrated bias elements | Tanmoy Roy, Nitin Chawla | 2025-03-04 |