Issued Patents 2025
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12205904 | Wafer-level design and wiring pattern for a semiconductor package | Yong Tae Kwon, Jun Kyu Lee, Dong Hoon OH, Kyeong Rok SHIN | 2025-01-21 |
| 12198997 | Semiconductor package comprising first molding layer and second molding layer with different thermal expansion coefficients | Dong Hoon OH, Yong Tae Kwon, Jun Kyu Lee, Kyeong Rok SHIN, Yong Woon Yeo | 2025-01-14 |