Issued Patents 2025
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400703 | Per bank refresh hazard avoidance for large scale memory | Chang Kian Tan, Saravanan Sethuraman | 2025-08-26 |
| 12360847 | Adaptive internal error scrubbing and error handling | Kjersten E. Criss, Rajat Agarwal, Omar Avelar Suarez, Subhankar Panda, Theodros Yigzaw +3 more | 2025-07-15 |
| 12347507 | Method and apparatus for memory chip row hammer threat backpressure signal and host side response | Bill Nale, Jongwon Lee, Sreenivas Mandava | 2025-07-01 |
| 12347818 | Logic die in a multi-chip package having a configurable physical interface to on-package memory | Narasimha Lanka, Lohit Yerva, Mohammad Mamunur Rashid | 2025-07-01 |
| 12340863 | Stacked memory chip solution with reduced package inputs/outputs (I/Os) | Chong J. Zhao, Shigeki Tomishima, James A. McCall, Dimitrios Ziakas | 2025-06-24 |
| 12321634 | Double fetch for long burst length memory data transfer | Bill Nale | 2025-06-03 |
| 12265723 | Per channel thermal management techniques for stacked memory | Chang Kian Tan, Ru Yin Ng, Saravanan Sethuraman | 2025-04-01 |
| 12259777 | Uncorrectable memory error prediction | Shen ZHOU, Xiaoming Du, Cong Li, Rajat Agarwal, Murugasamy K. Nachimuthu +3 more | 2025-03-25 |
| 12235720 | Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS) | Rajat Agarwal, Hsing-Min Chen, Wei-Pin Chen, Wei Wu, Jing Ling +7 more | 2025-02-25 |
| 12210456 | Dynamic random access memory (DRAM) with scalable meta data | — | 2025-01-28 |