Issued Patents 2025
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430057 | Dynamic multilevel memory system | Andrew M. Rudoff, Rajat Agarwal | 2025-09-30 |
| 12386748 | Selective fill for logical control over hardware multilevel memory | Rajat Agarwal, Sai Prashanth Muralidhara, Nishant Singh, Sharada Venkateswaran, Daniel W. Liu | 2025-08-12 |
| 12373287 | Distribution of error checking and correction (ECC) bits to allocate ECC bits for metadata | Rajat Agarwal, Bill Nale, James A. McCall | 2025-07-29 |
| 12271305 | Two-level main memory hierarchy management | Sai Prashanth Muralidhara, Alaa R. Alameldeen, Rajat Agarwal, Vivek Kozhikkottu | 2025-04-08 |
| 12242342 | Fast memory ECC error correction | Jing Ling, Rajat Agarwal | 2025-03-04 |
| 12235720 | Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS) | Rajat Agarwal, Hsing-Min Chen, Wei Wu, Jing Ling, Kuljit S. Bains +7 more | 2025-02-25 |