Issued Patents 2025
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12400871 | Metal lines with low via-to-via spacing | Somnath Ghosh, Hsueh-Chung Chen, Carl Radens, Lawrence A. Clevenger | 2025-08-26 |
| 12363965 | Stacked transistor layout for improved cell height scaling | Ruilong Xie, Nicholas Anthony Lanzillo, Albert M. Chu, Eric Miller, Lawrence A. Clevenger | 2025-07-15 |