CS

Charan V. Surisetty

AS Adeia Semiconductor Solutions: 2 patents #4 of 44Top 10%
📍 Clifton Park, NY: #38 of 92 inventorsTop 45%
🗺 New York: #1,351 of 9,062 inventorsTop 15%
Overall (2025): #134,240 of 469,880Top 30%
2
Patents 2025

Issued Patents 2025

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
12237328 Minimizing shorting between FinFET epitaxial regions Kangguo Cheng, Balasubramanian Pranatharthiharan, Alexander Reznicek 2025-02-25
12237368 Semiconductor structures including middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo 2025-02-25