Issued Patents 2024
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182038 | Methods and apparatus for allocation in a victim cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2024-12-31 |
| 12182573 | Processing device with vector transformation execution | Mujibur Rahman, Joseph Zbiciak | 2024-12-31 |
| 12175244 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2024-12-24 |
| 12159030 | Multicore shared cache operation engine | Kai Chirca, Matthew D. Pierson, David E. Smith | 2024-12-03 |
| 12147353 | Methods and apparatus for read-modify-write support in multi-banked data RAM cache for bank arbitration | Naveen Bhoria, Pete Michael Hippleheuser | 2024-11-19 |
| 12141073 | Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue | Naveen Bhoria, Pete Michael Hippleheuser | 2024-11-12 |
| 12141078 | Victim cache with dynamic allocation of entries | Naveen Bhoria, Pete Michael Hippleheuser | 2024-11-12 |
| 12141079 | Atomic operations and histogram operations in a cache pipeline | Naveen Bhoria, Pete Michael Hippleheuser | 2024-11-12 |
| 12135646 | Cache coherence shared state suppression | Abhijeet Ashok Chachad, David Matthew Thompson, Kai Chirca | 2024-11-05 |
| 12124728 | Quick clearing of registers | Duc Quang Bui, Soujanya Narnur | 2024-10-22 |
| 12118358 | One-dimensional zero padding in a stream of matrix elements | Son Hung Tran, Shyam Jagannathan | 2024-10-15 |
| 12105640 | Methods and apparatus for eviction in dual datapath victim cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2024-10-01 |
| 12105635 | Method and apparatus for vector permutation | Mujibur Rahman, Dheera Balasubramanian Samudrala, Peter Richard Dent, Duc Quang Bui | 2024-10-01 |
| 12099400 | Streaming engine with deferred exception reporting | Joseph Zbiciak, Duc Quang Bui, Kai Chirca | 2024-09-24 |
| 12099843 | Streaming address generation | Duc Quang Bui, Joseph Zbiciak, Sahithi KRISHNA, Soujanya Narnur | 2024-09-24 |
| 12086074 | Method and apparatus for permuting streamed data elements | Soujanya Narnur, Mujibur Rahman, Duc Quang Bui | 2024-09-10 |
| 12086064 | Aliased mode for cache controller | Abhijeet Ashok Chachad, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2024-09-10 |
| 12072814 | Methods and apparatus to facilitate read-modify-write support in a victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2024-08-27 |
| 12072812 | Highly integrated scalable, flexible DSP megamodule architecture | Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca, Naveen Bhoria +3 more | 2024-08-27 |
| 12072824 | Multicore bus architecture with non-blocking high performance transaction credit system | David Matthew Thompson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson | 2024-08-27 |
| 12067396 | Variable latency instructions | — | 2024-08-20 |
| 12061908 | Dual data streams sharing dual level two cache access ports to maximize bandwidth utilization | Joseph Zbiciak | 2024-08-13 |
| 12050914 | Cache management operations using streaming engine | Joseph Zbiciak, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu, Abhijeet Ashok Chachad +1 more | 2024-07-30 |
| 12045617 | Two-dimensional zero padding in a stream of matrix elements | William Franklin Leven, Asheesh Bhardwaj, Son Hung Tran | 2024-07-23 |
| 12045172 | Method and apparatus for implied bit handling in floating point multiplication | Mujibur Rahman | 2024-07-23 |