Issued Patents 2024
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12032961 | Vector maximum and minimum with indexing | Duc Quang Bui, Peter Richard Dent | 2024-07-09 |
| 12032490 | Method and apparatus for vector sorting | Mujibur Rahman | 2024-07-09 |
| 12019559 | Method and apparatus for dual issue multiply instructions | Mujibur Rahman | 2024-06-25 |
| 12007907 | Victim cache with write miss merging | Naveen Bhoria, Pete Michael Hippleheuser | 2024-06-11 |
| 12007904 | Method and apparatus for vector based matrix multiplication | Asheesh Bhardwaj, Mujibur Rahman | 2024-06-11 |
| 12001345 | Victim cache that supports draining write-miss entries | Naveen Bhoria, Pete Michael Hippleheuser | 2024-06-04 |
| 12001282 | Write control for read-modify-write operations in cache memory | Abhijeet Ashok Chachad, David Matthew Thompson, Daniel Wu | 2024-06-04 |
| 11994949 | Streaming engine with error detection, correction and restart | Joseph Zbiciak | 2024-05-28 |
| 11989072 | Controlling the number of powered vector lanes via a register field | Duc Quang Bui | 2024-05-21 |
| 11983559 | Streaming engine with short cut start instructions | Joseph Zbiciak | 2024-05-14 |
| 11977887 | System and method to control the number of active vector lanes in a processor | Duc Quang Bui | 2024-05-07 |
| 11972236 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2024-04-30 |
| 11960892 | Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor | Duc Quang Bui, Joseph Zbiciak | 2024-04-16 |
| 11960567 | Implementing fundamental computational primitives using a matrix multiplication accelerator (MMA) | Arthur John Redfern, Kai Chirca, Chenchi Luo, Zhenhua Yu | 2024-04-16 |
| 11940929 | Methods and apparatus to reduce read-modify-write cycles for non-aligned writes | Naveen Bhoria, Pete Michael Hippleheuser | 2024-03-26 |
| 11940930 | Methods and apparatus to facilitate atomic operations in victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2024-03-26 |
| 11940918 | Memory pipeline control in a hierarchical memory system | Abhijeet Ashok Chachad, Kai Chirca, David Matthew Thompson | 2024-03-26 |
| 11921643 | Method and apparatus for dual multiplication units in a data path | Mujibur Rahman, Soujanya Narnur | 2024-03-05 |
| 11922166 | Vector SIMD VLIW data path architecture | Duc Quang Bui, Mujibur Rahman, Joseph Zbiciak, Eric Biscondi, Peter Richard Dent +2 more | 2024-03-05 |
| 11921637 | Write streaming with cache write acknowledgment in a processor | Abhijeet Ashok Chachad, David Matthew Thompson | 2024-03-05 |
| 11907753 | Controller with caching and non-caching modes | Abhijeet Ashok Chachad, David Matthew Thompson | 2024-02-20 |
| 11907721 | Inserting predefined pad values into a stream of vectors | Asheesh Bhardwaj, Son Hung Tran | 2024-02-20 |
| 11900117 | Mechanism to queue multiple streams to run on streaming engine | Jonathan (Son) Hung Tran, Joseph Zbiciak | 2024-02-13 |
| 11900112 | Vector reverse | Duc Quang Bui | 2024-02-13 |
| 11886353 | Hybrid victim cache and write miss buffer with fence operation | Naveen Bhoria, Pete Michael Hippleheuser | 2024-01-30 |