NB

Naveen Bhoria

TI Texas Instruments: 20 patents #4 of 1,319Top 1%
📍 Plano, TX: #7 of 736 inventorsTop 1%
🗺 Texas: #70 of 16,704 inventorsTop 1%
Overall (2024): #2,371 of 561,600Top 1%
20
Patents 2024

Issued Patents 2024

Showing 1–20 of 20 patents

Patent #TitleCo-InventorsDate
12182038 Methods and apparatus for allocation in a victim cache system Timothy David Anderson, Pete Michael Hippleheuser 2024-12-31
12147353 Methods and apparatus for read-modify-write support in multi-banked data RAM cache for bank arbitration Timothy David Anderson, Pete Michael Hippleheuser 2024-11-19
12141079 Atomic operations and histogram operations in a cache pipeline Timothy David Anderson, Pete Michael Hippleheuser 2024-11-12
12141601 Global coherence operations Abhijeet Ashok Chachad, David Matthew Thompson, Neelima Muralidharan 2024-11-12
12141078 Victim cache with dynamic allocation of entries Timothy David Anderson, Pete Michael Hippleheuser 2024-11-12
12141073 Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue Timothy David Anderson, Pete Michael Hippleheuser 2024-11-12
12105640 Methods and apparatus for eviction in dual datapath victim cache system Timothy David Anderson, Pete Michael Hippleheuser 2024-10-01
12093690 Look-up table read Dheera Balasubramanian Samudrala, Duc Quang Bui, Alan L. Davis 2024-09-17
12086064 Aliased mode for cache controller Abhijeet Ashok Chachad, Timothy David Anderson, Pramod Kumar Swami, David Matthew Thompson, Neelima Muralidharan 2024-09-10
12072814 Methods and apparatus to facilitate read-modify-write support in a victim cache Timothy David Anderson, Pete Michael Hippleheuser 2024-08-27
12072812 Highly integrated scalable, flexible DSP megamodule architecture Timothy David Anderson, Joseph Zbiciak, Duc Quang Bui, Abhijeet Ashok Chachad, Kai Chirca +3 more 2024-08-27
12056051 Tag update bus for updated coherence state Abhijeet Ashok Chachad, David Matthew Thompson, Peter Michael Hippleheuser 2024-08-06
12038840 Multi-level cache security Abhijeet Ashok Chachad, David Matthew Thompson 2024-07-16
12007907 Victim cache with write miss merging Timothy David Anderson, Pete Michael Hippleheuser 2024-06-11
12001345 Victim cache that supports draining write-miss entries Timothy David Anderson, Pete Michael Hippleheuser 2024-06-04
11960891 Look-up table write Duc Quang Bui, Dheera Balasubramanian Samudrala 2024-04-16
11940929 Methods and apparatus to reduce read-modify-write cycles for non-aligned writes Timothy David Anderson, Pete Michael Hippleheuser 2024-03-26
11940930 Methods and apparatus to facilitate atomic operations in victim cache Timothy David Anderson, Pete Michael Hippleheuser 2024-03-26
11886353 Hybrid victim cache and write miss buffer with fence operation Timothy David Anderson, Pete Michael Hippleheuser 2024-01-30
11868272 Methods and apparatus for allocation in a victim cache system Timothy David Anderson, Pete Michael Hippleheuser 2024-01-09