Issued Patents 2024
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12148669 | Semiconductor device with S/D bottom isolation and methods of forming the same | Xusheng Wu, Huiling Shang | 2024-11-19 |
| 12142635 | Gate all-around semiconductor device | Ka-Hing Fung, Kuo-Cheng Ching | 2024-11-12 |
| 12068383 | Wrap around silicide for FinFETs | Kuo-Cheng Chiang, Chi-Wen Liu | 2024-08-20 |
| 12051729 | Bipolar junction transistor with gate over terminals | Ming-Shuan Li, Zi-Ang Su | 2024-07-30 |
| 12034077 | Method of forming source/drain regions with expanded widths | Kuo-Cheng Chiang, Chi-Wen Liu | 2024-07-09 |
| 11972981 | FinFET channel on oxide structures and related methods | Kuo-Cheng Ching, Ching-Wei Tsai | 2024-04-30 |
| 11961892 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge +2 more | 2024-04-16 |
| 11955554 | Method of fabricating a multi-gate device | Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu +1 more | 2024-04-09 |
| 11942548 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien | 2024-03-26 |
| 11929417 | Contacts for highly scaled transistors | Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge +2 more | 2024-03-12 |
| 11894275 | FinFET device having oxide region between vertical fin structures | Kuo-Cheng Ching | 2024-02-06 |