Issued Patents 2024
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12154851 | Method of forming a semiconductor device with inter-layer vias | Ching-Fang Chen, Jia-Jye Shen | 2024-11-26 |
| 12106034 | Rule check violation prediction systems and methods | Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong | 2024-10-01 |
| 12099793 | Rule check violation prediction systems and methods | Henry Lin, Szu-Ju Huang, Yin-An Chen, Amos Hong | 2024-09-24 |
| 12039249 | System and method for diagnosing design rule check violations | Yu-Chen Huang, Heng-Yi Lin | 2024-07-16 |
| 12039251 | Cell layout of semiconductor device | Huang-Yu Chen, Yun-Han Lee | 2024-07-16 |
| 12019971 | Static voltage drop (SIR) violation prediction systems and methods | Szu-Ju Huang, Shih-Yao Lin, Shih Feng Hung, Yin-An Chen | 2024-06-25 |
| 11928415 | Hard-to-fix (HTF) design rule check (DRC) violations prediction | Ching-Hsiang Hsu, Shih-Yao Lin | 2024-03-12 |
| 11900037 | Circuit synthesis optimization for implements on integrated circuit | Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Chih-Sheng Hou | 2024-02-13 |
| 11893334 | Method for optimizing floor plan for an integrated circuit | Shi-Wen TAN, Song Liu, Shih-Yao Lin, Wen-Yuan FANG | 2024-02-06 |