Issued Patents 2024
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12175175 | Systems and methods for generating synthesizable netlists from register transfer level designs | Boh-Yi Huang, Chao-Chun Lo, Tze-Chiang Huang, Chen-jih Lui | 2024-12-24 |
| 12169671 | Apparatus and method for mapping foundational components during design porting from one process technology to another process technology | Boh-Yi Huang, Chao-Chun Lo, Xiang Guo | 2024-12-17 |
| 11900035 | Attribute-point-based timing constraint formal verification | Chao-Chun Lo, Boh-Yi Huang | 2024-02-13 |
| 11900037 | Circuit synthesis optimization for implements on integrated circuit | Chao-Chun Lo, Boh-Yi Huang, Yi-Lin Chuang, Chih-Sheng Hou | 2024-02-13 |