Issued Patents 2024
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12131782 | 3D memory device including shared select gate connections between memory blocks | — | 2024-10-29 |
| 12125786 | Devices including stair step structures, and related memory devices and electronic systems | Paolo Tessariol, Graham R. Wolstenholme | 2024-10-22 |
| 12114499 | Block-on-block memory array architecture using bi-directional staircases | — | 2024-10-08 |
| 12080700 | Microelectronic devices including control logic regions | Kunal R. Parekh, Akira Goda | 2024-09-03 |
| 12080351 | Using non-segregated cells as drain-side select gates for sub-blocks in a memory device | — | 2024-09-03 |
| 12080360 | Reducing programming disturbance in memory devices | — | 2024-09-03 |
| 12068272 | Microelectronic devices having a memory array region, a control logic region, and signal routing structures | Akira Goda, Kunal R. Parekh | 2024-08-20 |
| 11915758 | Memory devices with four data line bias levels | Hao Thai Nguyen, Tomoko Ogura Iwasaki, Erwin E. Yu, Dheeraj Srinivasan, Sheyang Ning +2 more | 2024-02-27 |