Issued Patents 2024
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183396 | Memory array structures and methods of forming memory array structures | Dan Xu, Jun Xu, Erwin E. Yu, Paolo Tessariol | 2024-12-31 |
| 12144060 | Cellular signal mesh network | Kari Crane, Deepti Verma, Shruthi Kumara Vadivel, Sue-Fern Ng | 2024-11-12 |
| 12142334 | Health scan for content addressable memory | Manik Advani, Ramin Ghodsi | 2024-11-12 |
| 12142318 | Redundancy and majority voting in a key-value data storage system using content addressable memory | Tyler L. Betz, Manik Advani, Violante Moschiano | 2024-11-12 |
| 12112819 | Apparatus for determining memory cell data states | Sheyang Ning, Lawrence Celso Miranda, Ting Luo, Luyen Vu | 2024-10-08 |
| 12101932 | Microelectronic devices, and related memory devices and electronic systems | Erwin E. Yu, Surendranath C. Eruvuru, Yoshiaki Fukuzumi | 2024-09-24 |
| 12086458 | Programming content addressable memory | Manik Advani | 2024-09-10 |
| 12073895 | Ganged single level cell verify in a memory device | Eric N. Lee | 2024-08-27 |
| 12068037 | Managing sub-block erase operations in a memory sub-system | Kalyan C. Kavalipurapu, Erwin E. Yu, Hong-Yan Chen, Yunfei Xu | 2024-08-20 |
| 12014778 | In-line programming adjustment of a memory cell in a memory sub-system | Sheyang Ning, Lawrence Celso Miranda, Zhengyi Zhang | 2024-06-18 |
| 12001716 | Key-value data storage system using content addressable memory | Manik Advani | 2024-06-04 |
| 11961566 | Fast bit erase for upper tail tightening of threshold voltage distributions | Sheyang Ning, Lawrence Celso Miranda | 2024-04-16 |
| 11915758 | Memory devices with four data line bias levels | Hao Thai Nguyen, Erwin E. Yu, Dheeraj Srinivasan, Sheyang Ning, Lawrence Celso Miranda +2 more | 2024-02-27 |