Issued Patents 2024
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176293 | Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration | Lars Liebmann, Daniel Chanemougame, Paul Gutwin, Brian Tracy Cline, Xiaoqing Xu +1 more | 2024-12-24 |
| 12087640 | High density logic formation using multi-dimensional laser annealing | H. Jim Fulford, Mark I. Gardner, Lars Liebmann, Daniel Chanemougame | 2024-09-10 |
| 12051638 | Integrated high efficiency transistor cooling | Daniel Chanemougame, Lars Liebmann, Paul Gutwin | 2024-07-30 |
| 12040271 | Power delivery network for CFET with buried power rails | Lars Liebmann, Daniel Chanemougame, Anton J. deVilliers | 2024-07-16 |
| 12020990 | Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks | Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, Mark I. Gardner, H. Jim Fulford +1 more | 2024-06-25 |
| 12014984 | Method of manufacturing a semiconductor apparatus having stacked devices | Lars Liebmann, Anton J. deVilliers | 2024-06-18 |
| 12002862 | Inter-level handshake for dense 3D logic integration | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2024-06-04 |
| 11961802 | Power-tap pass-through to connect a buried power rail to front-side power distribution network | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2024-04-16 |
| 11923364 | Double cross-couple for two-row flip-flop using CFET | Lars Liebmann, Daniel Chanemougame, Paul Gutwin | 2024-03-05 |
| 11901360 | Architecture design and process for manufacturing monolithically integrated 3D CMOS logic and memory | Lars Liebmann, Anton J. deVilliers, Kandabara Tapily | 2024-02-13 |