HR

Hari Anand Ravi

CS Cadence Design Systems: 3 patents #5 of 141Top 4%
📍 Survanagiri, NJ: #1 of 2 inventorsTop 50%
Overall (2024): #85,367 of 561,600Top 20%
3
Patents 2024

Issued Patents 2024

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
12183427 System and method for write clock double data rate duty cycle correction Sachin Ramesh Gugwad 2024-12-31
12184286 Clock duty cycle measurement Prakash Kumar Lenka, Jitendra Kumar Yadav 2024-12-31
11979262 Identifying and training floating tap for decision feedback equalization Sachin Ramesh Gugwad 2024-05-07