JY

Jitendra Kumar Yadav

CS Cadence Design Systems: 2 patents #13 of 141Top 10%
CI Ciena: 1 patents #63 of 221Top 30%
📍 Bhopal, MA: #1 of 1 inventorsTop 100%
Overall (2024): #81,295 of 561,600Top 15%
3
Patents 2024

Issued Patents 2024

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
12184286 Clock duty cycle measurement Prakash Kumar Lenka, Hari Anand Ravi 2024-12-31
12081407 Updating configuration settings of network elements when a network is changed to a planned topology Dale Frederick Zacharias 2024-09-03
11876521 Dynamically updated delay line Hajee Mohammed Shuaeb Fazeel, Thomas Evan Wilson 2024-01-16