Issued Patents 2023
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11844217 | Methods for forming multi-layer vertical nor-type memory string arrays | Scott Brad Herner, Wu-Yi Henry Chien, Jie Zhou | 2023-12-12 |
| 11844204 | Process for preparing a channel region of a thin-film transistor in a 3-dimensional thin-film transistor array | Vinod R. Purayath, Jie Zhou, Wu-Yi Henry Chien | 2023-12-12 |
| 11839086 | 3-dimensional memory string array of thin-film ferroelectric transistors | Christopher J. Petti, Vinod R. Purayath, George Samachisa, Wu-Yi Henry Chien | 2023-12-05 |
| 11817156 | Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates | — | 2023-11-14 |
| 11800716 | Method for in situ preparation of antimony-doped silicon and silicon germanium films | Scott Brad Herner | 2023-10-24 |
| 11758727 | Three-dimensional vertical nor flash thin-film transistor strings | Tianhong Yan | 2023-09-12 |
| 11751388 | 3-dimensional nor strings with segmented shared source regions | Raul-Adrian Cernea | 2023-09-05 |
| 11751392 | Fabrication method for a 3-dimensional NOR memory array | Scott Brad Herner, Wu-Yi Henry Chien | 2023-09-05 |
| 11751391 | Methods for fabricating a 3-dimensional memory structure of nor memory strings | Vinod R. Purayath, Yosuke Nosho, Shohei Kamisaka, Michiru Nakane | 2023-09-05 |
| 11749344 | Three-dimensional vertical nor flash thin-film transistor strings | — | 2023-09-05 |
| 11730000 | 3-dimensional nor string arrays in segmented stacks | Wu-Yi Henry Chien | 2023-08-15 |
| 11729980 | 3-dimensional NOR memory array architecture and methods for fabrication thereof | Scott Brad Herner, Wu-Yi Henry Chien | 2023-08-15 |
| 11710729 | Wafer bonding in fabrication of 3-dimensional NOR memory circuits | Scott Brad Herner | 2023-07-25 |
| 11705496 | Charge-trapping layer with optimized number of charge-trapping sites for fast program and erase of a memory cell in a 3-dimensional NOR memory string array | Wu-Yi Henry Chien, Scott Brad Herner | 2023-07-18 |
| 11675500 | High capacity memory circuit with low effective latency | Youn Cheul Kim, Richard S. Chernicoff, Khandker N. Quader, Robert Norman, Tianhong Yan +1 more | 2023-06-13 |
| 11670620 | Device with embedded high-bandwidth, high-capacity memory using wafer bonding | Khandker N. Quader, Robert Norman, Frank Sai-keung Lee, Christopher J. Petti, Scott Brad Herner +3 more | 2023-06-06 |
| 11610914 | Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays | Tianhong Yan, Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien | 2023-03-21 |
| 11610909 | Processes for forming 3-dimensional horizontal NOR memory arrays | Wu-Yi Henry Chien | 2023-03-21 |
| 11580038 | Quasi-volatile system-level memory | Robert Norman, Khandker N. Quader, Frank Sai-keung Lee, Richard S. Chernicoff, Youn Cheul Kim +1 more | 2023-02-14 |
| 11561911 | Channel controller for shared memory access | Robert Norman, Richard S. Chernicoff | 2023-01-24 |
| 11557606 | Epitaxial monocrystalline channel for storage transistors in 3-dimensional memory structures and methods for formation thereof | Chenming Hu, Wu-Yi Henry Chien | 2023-01-17 |