Issued Patents 2023
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11837296 | Non-volatile memory with adjusted bit line voltage during verify | Yu-Chung Lien, Ohwon Kwon | 2023-12-05 |
| 11790655 | Video sampling method and apparatus using the same | Wei WEN, Jianhua Fan | 2023-10-17 |
| 11791001 | Non-volatile memory with updating of read compare voltages based on measured current | Yi Song, Dengtao Zhao | 2023-10-17 |
| 11790994 | Non-volatile memory with reverse state program | Ming Wang, Liang Li | 2023-10-17 |
| 11756630 | Obtaining threshold voltage measurements for memory cells based on a user read mode | Liang Li, Qianqian Yu, Loc Tu | 2023-09-12 |
| 11758718 | Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines | Yu-Chung Lien, Abhijith Prakash, Keyur Payak, Huai-Yuan Tseng, Shinsuke Yada +1 more | 2023-09-12 |
| 11705206 | Modifying program and erase parameters for single-bit memory cells to improve single-bit/multi-bit hybrid ratio | Abu Naser Zainuddin, Jia Li, Bo Lei | 2023-07-18 |
| 11664075 | Sub-block programming mode with multi-tier block | Yu-Chung Lien, Tomer Eliash | 2023-05-30 |
| 11657883 | Isolating problematic memory planes to avoid neighbor plan disturb | Ke Zhang, Liang Li | 2023-05-23 |
| 11631686 | Three-dimensional memory array including dual work function floating gates and method of making the same | Ramy Nashed Bassely Said, Yanli Zhang, Raghuveer S. Makala, Senaka Kanakamedala | 2023-04-18 |
| 11587619 | Block configuration for memory device with separate sub-blocks | Yu-Chung Lien, Deepanshu Dutta | 2023-02-21 |