Issued Patents 2023
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11749353 | Managing sub-block erase operations in a memory sub-system | Kalyan C. Kavalipurapu, Tomoko Ogura Iwasaki, Hong-Yan Chen, Yunfei Xu | 2023-09-05 |
| 11562791 | Memory devices with four data line bias levels | Hao Thai Nguyen, Tomoko Ogura Iwasaki, Dheeraj Srinivasan, Sheyang Ning, Lawrence Celso Miranda +2 more | 2023-01-24 |
| 11557341 | Memory array structures and methods for determination of resistive characteristics of access lines | Dan Xu, Jun Xu, Paolo Tessariol, Tomoko Ogura Iwasaki | 2023-01-17 |
| 11557351 | Sense circuit to sense two states of a memory cell | Luyen Vu, Jeffrey Ming-Hung Tsai | 2023-01-17 |