Issued Patents 2023
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11842762 | System application of DRAM component with cache mode | Frederick A. Ware, Michael Raymond Miller, Collins Williams | 2023-12-12 |
| 11842761 | Memory system with multiple open rows per bank | John Eric Linstadt, Liji Gopalakrishnan | 2023-12-12 |
| 11823734 | Dram device with multiple voltage domains | — | 2023-11-21 |
| 11822822 | Memory component having internal read-modify-write operation | Frederick A. Ware | 2023-11-21 |
| 11804250 | Memory with deferred fractional row activation | James E. Harris, Frederick A. Ware, Ian Shaeffer | 2023-10-31 |
| 11790973 | Memory component with efficient write operations | Frederick A. Ware, John Eric Linstadt, Brent Haukness, Kenneth L. Wright | 2023-10-17 |
| 11775213 | Stacked memory device with paired channels | — | 2023-10-03 |
| 11653476 | Memory subsystem for a cryogenic digital system | Frederick A. Ware, John Eric Linstadt | 2023-05-16 |
| 11646090 | DRAM retention test method for dynamic error correction | Ely Tsern, Frederick A. Ware, Suresh Rajan | 2023-05-09 |
| 11645212 | Dynamic processing speed | Steven C. Woo, Joseph James Tringali, Pooneh Safayenikoo | 2023-05-09 |
| 11600349 | Testing through-silicon-vias | William N. Ng, Frederick A. Ware | 2023-03-07 |
| 11568929 | 2T-1R architecture for resistive RAM | Deepak C. Sekar, Wayne F. Ellis, Brent Haukness, Gary B. Bronner | 2023-01-31 |