Issued Patents 2023
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11823762 | Low power memory system using dual input-output voltage supplies | Jungwon Suh, Joon Young Park | 2023-11-21 |
| 11662765 | System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces | Vaishnav Srinivas, Christophe Avoinne, Xavier Leloup, Michael Jäger | 2023-05-30 |
| 11551730 | Low power memory system using dual input-output voltage supplies | Jungwon Suh, Joon Young Park | 2023-01-10 |