Issued Patents 2023
Showing 1–1 of 1 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11662765 | System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces | Mahalingam Nagarajan, Vaishnav Srinivas, Christophe Avoinne, Michael Jäger | 2023-05-30 |