PW

Po-Hsun Wu

ET Elite Semiconductor Microelectronics Technology: 2 patents #2 of 15Top 15%
IT ITRI: 2 patents #43 of 796Top 6%
Overall (2023): #41,022 of 537,848Top 8%
4
Patents 2023

Issued Patents 2023

Showing 1–4 of 4 patents

Patent #TitleCo-InventorsDate
11727968 Method for self-calibrating tDQSCK that is skew between rising edge of memory clock signal and rising edge of DQS signal during read operation and associated signal processing circuit Jen-Shou Hsu 2023-08-15
11694337 Processing path generating method and device Meng-Chiou Liao, Chang-Lin Wang, Chin-Ming Chen, Chien-Yi Lee 2023-07-04
11685008 Dodge method of machining path and machining system Chun-Ting Chen, Cheng-Wei Wang, Chien-Chih Liao, Jen-Ji Wang 2023-06-27
11545200 Data control circuit for increasing maximum and minimum tolerance values of skew between DQS signal and clock signal during write operation and associated memory device Jen-Shou Hsu 2023-01-03