JH

Jen-Shou Hsu

ET Elite Semiconductor Microelectronics Technology: 2 patents #2 of 15Top 15%
Overall (2023): #145,534 of 537,848Top 30%
2
Patents 2023

Issued Patents 2023

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
11727968 Method for self-calibrating tDQSCK that is skew between rising edge of memory clock signal and rising edge of DQS signal during read operation and associated signal processing circuit Po-Hsun Wu 2023-08-15
11545200 Data control circuit for increasing maximum and minimum tolerance values of skew between DQS signal and clock signal during write operation and associated memory device Po-Hsun Wu 2023-01-03