Issued Patents 2022
Showing 1–25 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11507513 | Methods and apparatus to facilitate an atomic operation and/or a histogram operation in cache pipeline | Naveen Bhoria, Pete Michael Hippleheuser | 2022-11-22 |
| 11501024 | Secure master and secure guest endpoint security firewall | Joseph Zbiciak, Matthew D. Pierson, Kai Chirca | 2022-11-15 |
| 11500631 | Method and apparatus for implied bit handling in floating point multiplication | Mujibur Rahman | 2022-11-15 |
| 11494224 | Controller with caching and non-caching modes | Abhijeet Ashok Chachad, David Matthew Thompson | 2022-11-08 |
| 11487616 | Write control for read-modify-write operations in cache memory | Abhijeet Ashok Chachad, David Matthew Thompson, Daniel Wu | 2022-11-01 |
| 11461106 | Programmable event testing | Kai Chirca | 2022-10-04 |
| 11461236 | Methods and apparatus for allocation in a victim cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2022-10-04 |
| 11461096 | Method and apparatus for vector sorting using vector permutation logic | Mujibur Rahman | 2022-10-04 |
| 11449432 | Methods and apparatus for eviction in dual datapath victim cache system | Naveen Bhoria, Pete Michael Hippleheuser | 2022-09-20 |
| 11449336 | Method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof | Duc Quang Bui, Alan L. Davis, Dheera Balasubramanian Samudrala | 2022-09-20 |
| 11442868 | Aggressive write flush scheme for a victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2022-09-13 |
| 11442709 | Nested loop control | Kai Chirca, Todd T. Hahn, Alan L. Davis | 2022-09-13 |
| 11429387 | Streaming engine with stream metadata saving for context switching | Joseph Zbiciak | 2022-08-30 |
| 11422938 | Multicore, multibank, fully concurrent coherence controller | Matthew D. Pierson, Kai Chirca | 2022-08-23 |
| 11403229 | Methods and apparatus to facilitate atomic operations in victim cache | Naveen Bhoria, Pete Michael Hippleheuser | 2022-08-02 |
| 11403110 | Storing a result of a first instruction of an execute packet in a holding register prior to completion of a second instruction of the execute packet | Kai Chirca, Paul Daniel Gauvreau | 2022-08-02 |
| 11397583 | Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor | Duc Quang Bui, Joseph Zbiciak | 2022-07-26 |
| 11392316 | System and method for predication handling | Duc Quang Bui, Joseph Zbiciak, Sahithi KRISHNA, Soujanya Narnur, Alan D. Davis | 2022-07-19 |
| 11392498 | Aliased mode for cache controller | Abhijeet Ashok Chachad, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2022-07-19 |
| 11372646 | Exit history based branch prediction | Kai Chirca, David E. Smith, Paul Daniel Gauvreau | 2022-06-28 |
| 11360905 | Write merging on stores with different privilege levels | Naveen Bhoria, Pete Michael Hippleheuser | 2022-06-14 |
| 11360536 | Controlling the number of powered vector lanes via a register field | Duc Quang Bui | 2022-06-14 |
| 11347649 | Victim cache with write miss merging | Naveen Bhoria, Pete Michael Hippleheuser | 2022-05-31 |
| 11347503 | Method and apparatus for vector based matrix multiplication | Asheesh Bhardwaj, Mujibur Rahman | 2022-05-31 |
| 11341052 | Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect | Kai Chirca, Matthew D. Pierson, Joseph Zbiciak | 2022-05-24 |