| 11494224 |
Controller with caching and non-caching modes |
Abhijeet Ashok Chachad, Timothy David Anderson |
2022-11-08 |
| 11487616 |
Write control for read-modify-write operations in cache memory |
Abhijeet Ashok Chachad, Timothy David Anderson, Daniel Wu |
2022-11-01 |
| 11461127 |
Pipeline arbitration |
Abhijeet Ashok Chachad |
2022-10-04 |
| 11416334 |
Handling non-correctable errors |
Abhijeet Ashok Chachad |
2022-08-16 |
| 11392498 |
Aliased mode for cache controller |
Abhijeet Ashok Chachad, Timothy David Anderson, Pramod Kumar Swami, Naveen Bhoria, Neelima Muralidharan |
2022-07-19 |
| 11321268 |
Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels |
Timothy David Anderson, Joseph Zbiciak, Abhijeet Ashok Chachad, Kai Chirca, Matthew D. Pierson |
2022-05-03 |
| 11321248 |
Multiple-requestor memory access pipeline and arbiter |
Abhijeet Ashok Chachad |
2022-05-03 |
| 11314660 |
Prefetch kill and revival in an instruction cache |
Bipin Prasad Heremagalur Ramaprasad, Abhijeet Ashok Chachad, Hung Ong |
2022-04-26 |
| 11314644 |
Cache size change |
Abhijeet Ashok Chachad, Naveen Bhoria, Neelima Muralidharan |
2022-04-26 |
| 11307987 |
Tag update bus for updated coherence state |
Abhijeet Ashok Chachad, Naveen Bhoria, Peter Michael Hippleheuser |
2022-04-19 |
| 11307858 |
Cache preload operations using streaming engine |
Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more |
2022-04-19 |
| 11294707 |
Global coherence operations |
Abhijeet Ashok Chachad, Naveen Bhoria, Neelima Muralidharan |
2022-04-05 |
| 11249842 |
Error correcting codes for multi-master memory controller |
Abhijeet Ashok Chachad, Son Hung Tran |
2022-02-15 |
| 11243883 |
Cache coherence shared state suppression |
Abhijeet Ashok Chachad, Timothy David Anderson, Kai Chirca |
2022-02-08 |
| 11237905 |
Pipelined read-modify-write operations in cache memory |
Abhijeet Ashok Chachad, Daniel Wu |
2022-02-01 |