Issued Patents 2022
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11537532 | Lookahead priority collection to support priority elevation | Raguram Damodaran, Ramakrishnan Venkatasubramanian, Joseph Zbiciak | 2022-12-27 |
| 11494224 | Controller with caching and non-caching modes | Timothy David Anderson, David Matthew Thompson | 2022-11-08 |
| 11487616 | Write control for read-modify-write operations in cache memory | Timothy David Anderson, David Matthew Thompson, Daniel Wu | 2022-11-01 |
| 11461127 | Pipeline arbitration | David Matthew Thompson | 2022-10-04 |
| 11416334 | Handling non-correctable errors | David Matthew Thompson | 2022-08-16 |
| 11392498 | Aliased mode for cache controller | Timothy David Anderson, Pramod Kumar Swami, Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2022-07-19 |
| 11321248 | Multiple-requestor memory access pipeline and arbiter | David Matthew Thompson | 2022-05-03 |
| 11321268 | Multicore bus architecture with wire reduction and physical congestion minimization via shared transaction channels | David Matthew Thompson, Timothy David Anderson, Joseph Zbiciak, Kai Chirca, Matthew D. Pierson | 2022-05-03 |
| 11314644 | Cache size change | Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2022-04-26 |
| 11314660 | Prefetch kill and revival in an instruction cache | Bipin Prasad Heremagalur Ramaprasad, David Matthew Thompson, Hung Ong | 2022-04-26 |
| 11307858 | Cache preload operations using streaming engine | Joseph Zbiciak, Timothy David Anderson, Jonathan (Son) Hung Tran, Kai Chirca, Daniel Wu +1 more | 2022-04-19 |
| 11307987 | Tag update bus for updated coherence state | David Matthew Thompson, Naveen Bhoria, Peter Michael Hippleheuser | 2022-04-19 |
| 11294707 | Global coherence operations | Naveen Bhoria, David Matthew Thompson, Neelima Muralidharan | 2022-04-05 |
| 11249842 | Error correcting codes for multi-master memory controller | David Matthew Thompson, Son Hung Tran | 2022-02-15 |
| 11243883 | Cache coherence shared state suppression | David Matthew Thompson, Timothy David Anderson, Kai Chirca | 2022-02-08 |
| 11237905 | Pipelined read-modify-write operations in cache memory | David Matthew Thompson, Daniel Wu | 2022-02-01 |