Issued Patents 2022
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11416165 | Low synch dedicated accelerator with in-memory computation capability | Sasikanth Manipatruni, Victor W. Lee, Huseyin Ekin Sumbul, Gregory K. Chen, Raghavan Kumar +4 more | 2022-08-16 |
| 11394387 | 2-input NAND gate with non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2022-07-19 |
| 11381244 | Low power ferroelectric based majority logic gate multiplier | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2022-07-05 |
| 11373727 | Apparatus for improving memory bandwidth through read and restore decoupling | Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2022-06-28 |
| 11374575 | Majority logic gate with non-linear input capacitors and conditioning logic | Rajeev Kumar Dokania, Rafael Rios, Ikenna Odinaka, Robert Menezes, Ramamoorthy Ramesh +1 more | 2022-06-28 |
| 11374574 | Linear input and non-linear output threshold logic gate | Sasikanth Manipatruni, Robert Menezes, Yuan-Sheng Fang, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2022-06-28 |
| 11373728 | Method for improving memory bandwidth through read and restore decoupling | Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2022-06-28 |
| 11366589 | Efficient method for improving memory bandwidth through read and restore decoupling using restore buffer | Christopher B. Wilkerson, Rajeev Kumar Dokania, Sasikanth Manipatruni | 2022-06-21 |
| 11347994 | Weight prefetch for in-memory neural network execution | Sasikanth Manipatruni, Victor W. Lee, Huseyin Ekin Sumbul, Gregory K. Chen, Raghavan Kumar +4 more | 2022-05-31 |
| 11303280 | Ferroelectric or paraelectric based sequential circuit | Ikenna Odinaka, Rajeev Kumar Dokania, Rafael Rios, Sasikanth Manipatruni | 2022-04-12 |
| 11295796 | Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection | Christopher B. Wilkerson, Sasikanth Manipatruni, Rajeev Kumar Dokania | 2022-04-05 |
| 11296708 | Low power ferroelectric based majority logic gate adder | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2022-04-05 |
| 11294985 | Efficient analog in-memory matrix multiplication processor | Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young, Ram Krishnamurthy | 2022-04-05 |
| 11290111 | Majority logic gate based and-or-invert logic gate with non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2022-03-29 |
| 11290112 | Majority logic gate based XOR logic gate with non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2022-03-29 |
| 11289497 | Integration method of ferroelectric memory array | Gaurav Thareja, Sasikanth Manipatruni, Rajeev Kumar Dokania, Ramamoorthy Ramesh | 2022-03-29 |
| 11283453 | Low power ferroelectric based majority logic gate carry propagate and serial adder | Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja +1 more | 2022-03-22 |
| 11277137 | Majority logic gate with non-linear input capacitors | Sasikanth Manipatruni, Rafael Rios, Neal Reynolds, Ikenna Odinaka, Robert Menezes +2 more | 2022-03-15 |