| 11509312 |
Apparatus and a method for synchronizing output clock signals across a plurality of phase-locked loops |
Soon Chieh Lim, Ging Yeon Mark Wong, How Hwan WONG |
2022-11-22 |
| 11500412 |
Techniques for clock signal transmission in integrated circuits and interposers |
Jeffrey Christopher Chromczak, Chooi Pei Lim, Lai Guan Tang, MD Altaf Hossain, Dheeraj Subbareddy +1 more |
2022-11-15 |
| 11449247 |
Periphery shoreline augmentation for integrated circuits |
Curtis Wortman, Jeffrey Erik Schulz |
2022-09-20 |
| 11442878 |
Memory sequencer system and a method of memory sequencing using thereof |
Soon Chieh Lim |
2022-09-13 |
| 11373694 |
Generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device |
Soon Chieh Lim, Tat Hin Tan |
2022-06-28 |
| 11349481 |
I/O transmitter circuitry for supporting multi-modes serialization |
Selvakumar Sivarajah, Soon Chieh Lim, Tze Jian CHOW |
2022-05-31 |
| 11301412 |
Scaling interface architecture between memory and programmable logic |
— |
2022-04-12 |
| 11226925 |
Scalable 2.5D interface circuitry |
Arifur Rahman |
2022-01-18 |
| 11216397 |
Translation circuitry for an interconnection in an active interposer of a semiconductor package |
Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy, MD Altaf Hossain |
2022-01-04 |