SM

Santosh Subhaschandra Malagi

CS Cadence Design Systems: 3 patents #8 of 234Top 4%
📍 Endicott, NY: #1 of 21 inventorsTop 5%
🗺 New York: #1,255 of 12,227 inventorsTop 15%
Overall (2022): #63,739 of 548,613Top 15%
3
Patents 2022

Issued Patents 2022

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
11461520 SDD ATPG using fault rules files, SDF and node slack for testing an IC chip Arvind Chokhani, Joseph M. Swenton 2022-10-04
11435401 Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip Arvind Chokhani, Joseph Michael Swenton 2022-09-06
11429776 Fault rules files for testing an IC chip Arvind Chokhani, Joseph Michael Swenton 2022-08-30