JS

Joseph Michael Swenton

CS Cadence Design Systems: 2 patents #18 of 234Top 8%
📍 Owego, NY: #2 of 8 inventorsTop 25%
🗺 New York: #2,032 of 12,227 inventorsTop 20%
Overall (2022): #143,680 of 548,613Top 30%
2
Patents 2022

Issued Patents 2022

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
11435401 Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip Arvind Chokhani, Santosh Subhaschandra Malagi 2022-09-06
11429776 Fault rules files for testing an IC chip Arvind Chokhani, Santosh Subhaschandra Malagi 2022-08-30