AC

Arvind Chokhani

CS Cadence Design Systems: 3 patents #8 of 234Top 4%
📍 Sachse, TX: #7 of 96 inventorsTop 8%
🗺 Texas: #1,731 of 16,454 inventorsTop 15%
Overall (2022): #89,002 of 548,613Top 20%
3
Patents 2022

Issued Patents 2022

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
11461520 SDD ATPG using fault rules files, SDF and node slack for testing an IC chip Joseph M. Swenton, Santosh Subhaschandra Malagi 2022-10-04
11435401 Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip Joseph Michael Swenton, Santosh Subhaschandra Malagi 2022-09-06
11429776 Fault rules files for testing an IC chip Joseph Michael Swenton, Santosh Subhaschandra Malagi 2022-08-30