Issued Patents 2021
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11189791 | Integrated circuit and fabrication method thereof | Ming-Che Ku, Jiun-Yu Tsai | 2021-11-30 |
| 11189659 | Techniques for MRAM MTJ top electrode to via interface | Harry-Hak-Lay Chuang, Jiunyu Tsai, Sheng-Huang Huang | 2021-11-30 |
| 11121308 | Sidewall spacer structure for memory cell | Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Tsung-Hsueh Yang, Yuan-Tai Tseng +2 more | 2021-09-14 |
| 11075335 | Techniques for MRAM MTJ top electrode connection | Harry-Hak-Lay Chuang, Chen-Pin Hsu, Wen-Chun You, Sheng-Chang Chen, Tsun Chung Tu +2 more | 2021-07-27 |
| 11063208 | Embedded MRAM fabrication process for ion beam etching with protection by top electrode spacer | Harry-Hak-Lay Chuang, Jun Chen | 2021-07-13 |
| 11043531 | Semiconductor structure and manufacturing method of the same | Alexander Kalnitsky, Sheng-Huang Huang, Harry-Hak-Lay Chuang, Jiunyu Tsai | 2021-06-22 |
| 11031543 | Via landing enhancement for memory device | Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh | 2021-06-08 |
| 11005032 | Techniques for MRAM MTJ top electrode to metal layer interface including spacer | Harry-Hak-Lay Chuang, Jiunyu Tsai, Sheng-Huang Huang | 2021-05-11 |
| 10998377 | Semiconductor structure and manufacturing method of the same | Harry-Hak-Lay Chuang, Sheng-Huang Huang, Keng-Ming Kuo | 2021-05-04 |
| 10957847 | Multilayered spacer structure for a magnetic tunneling junction and method of manufacturing | Harry-Hak-Lay Chuang, Sheng-Huang Huang | 2021-03-23 |
| 10937957 | Manufacturing techniques and corresponding devices for magnetic tunnel junction devices | Harry-Hak-Lay Chuang, Tien-Wei Chiang, Wen-Chun You | 2021-03-02 |