Issued Patents 2021
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11199866 | Voltage regulator with power rail tracking | Haruki Mori, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen +2 more | 2021-12-14 |
| 11183234 | Bitcell supporting bit-write-mask function | Yen-Huei Chen, Yi-Hsin Nien | 2021-11-23 |
| 11176997 | Memory cell | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin | 2021-11-16 |
| 11152301 | Memory cell having multi-level word line | Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao | 2021-10-19 |
| 11152057 | SRAM memory | Cheng Chun Dai, Chih-Yu Lin, Yen-Huei Chen, Hiroki Noguchi | 2021-10-19 |
| 11139040 | Method of detecting address decoding error | Ching-Wei Wu, Chun-Hao Chang | 2021-10-05 |
| 11088151 | 4Cpp SRAM cell and array | Chia-En Huang, Yen-Huei Chen, Yih Wang | 2021-08-10 |
| 11074966 | Method and system to balance ground bounce | Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2021-07-27 |
| 11062739 | Semiconductor chip having memory and logic cells | Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2021-07-13 |
| 11042688 | Method of certifying safety levels of semiconductor memories in integrated circuits | Ching-Wei Wu, Ming-En Bu, He-Zhou WAN, Xiu-Li YANG | 2021-06-22 |
| 11037644 | Testing circuit, testing method, and apparatus for testing multi-port random access memory | Yen-Huei Chen | 2021-06-15 |
| 11024633 | SRAM cell word line structure with reduced RC effects | Wei Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao | 2021-06-01 |
| 11018142 | Memory cell and method of manufacturing the same | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Yasutoshi Okuno | 2021-05-25 |
| 10991420 | Semiconductor device including distributed write driving arrangement and method of operating same | Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen | 2021-04-27 |
| 10978144 | Integrated circuit and operating method thereof | Chia-En Huang, Jui-Che Tsai, Yen-Huei Chen, Yih Wang | 2021-04-13 |
| 10971217 | SRAM cell for interleaved wordline scheme | Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil | 2021-04-06 |
| 10964389 | Memory cell | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Chien-Chen Lin | 2021-03-30 |
| 10964683 | Memory array circuit and method of manufacturing the same | Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Sahil Preet Singh | 2021-03-30 |
| 10950298 | Mixed threshold voltage memory array | Wei Zhao, Chih-Yu Lin | 2021-03-16 |
| 10943667 | Memory device | Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Hiroki Noguchi, Wei Zhao | 2021-03-09 |
| 10892008 | Multi word line assertion | Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Wei Zhao | 2021-01-12 |
| 10885973 | Memory device and method of controlling memory device | Yen-Huei Chen | 2021-01-05 |