Issued Patents 2021
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10957651 | Package level power gating | Luke Y. Chang, Narayan Kulshrestha | 2021-03-23 |
| 10943882 | IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures | Jayprakash Chipalkatti, Zuhair Bokharey, Brian Schieck, Julie Lam, Prashant Pathak | 2021-03-09 |