| 11204977 |
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs |
Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more |
2021-12-21 |
| 11182337 |
Computing efficient cross channel operations in parallel computing machines using systolic arrays |
Subramaniam Maiyuran, Jorge Parra, Chandra Gurram |
2021-11-23 |
| 11157238 |
Use of a single instruction set architecture (ISA) instruction for vector normalization |
Abhishek Rhisheekesan, Shashank Lakshminarayana, Subramaniam Maiyuran |
2021-10-26 |
| 11127108 |
Sparse matrix optimization mechanism |
Namita Sharma, Biju P. Simon, Tovinakere D. Vivek |
2021-09-21 |
| 11042370 |
Instruction and logic for systolic dot product with accumulate |
Subramaniam Maiyuran, Guei-Yuan Lueh, Ashutosh Garg, Chandra Gurram, Jorge Parra +10 more |
2021-06-22 |
| 11010163 |
Hierarchical general register file (GRF) for execution block |
Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu +7 more |
2021-05-18 |
| 10990409 |
Control flow mechanism for execution of graphics processor instructions using active channel packing |
Subramaniam Maiyuran, Guei-Yuan Lueh, Gang Chen, Ananda V. Kommaraju, Joy Chandra +10 more |
2021-04-27 |
| 10983794 |
Register sharing mechanism |
Guei-Yuan Lueh, Subramaniam Maiyuran, Weiyu Chen, Konrad Trifunovic, Chandra Gurram +3 more |
2021-04-20 |