Issued Patents 2021
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11210094 | Method and apparatus for minimally intrusive instruction pointer-aware processing resource activity profiling | Michael Cole, Alexandr Kurylev, Vikranth Vemulapalli, Sriharsha Vadlamani, Piotr Reiter | 2021-12-28 |
| 11204977 | Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs | Jorge Parra, Supratim Pal, Ashutosh Garg, Shubra Marwaha, Chandra Gurram +3 more | 2021-12-21 |
| 11188618 | Sparse matrix multiplication acceleration mechanism | Mathew Nevin, Jorge Parra, Ashutosh Garg, Shubra Marwaha, Shubh Shah | 2021-11-30 |
| 11163578 | Systems and methods for reducing register bank conflicts based on a software hint bit causing a hardware thread switch | Buqi Cheng, Wei-Yu Chen, Guei-Yuan Lueh, Chandra Gurram | 2021-11-02 |
| 11157238 | Use of a single instruction set architecture (ISA) instruction for vector normalization | Abhishek Rhisheekesan, Supratim Pal, Shashank Lakshminarayana | 2021-10-26 |
| 11087542 | Replicating primitives across multiple viewports | Kalyan Kumar BHIRAVABHATLA, Robert M. Toth, Tomasz Janczak | 2021-08-10 |
| 11042370 | Instruction and logic for systolic dot product with accumulate | Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Chandra Gurram, Jorge Parra +10 more | 2021-06-22 |
| 10983794 | Register sharing mechanism | Guei-Yuan Lueh, Weiyu Chen, Konrad Trifunovic, Supratim Pal, Chandra Gurram +3 more | 2021-04-20 |
| 10963389 | Instruction prefetch mechanism | Vasileios Porpodas, Guei-Yuan Lueh, Wei-Yu Chen | 2021-03-30 |