| 11205125 |
Scheduler and simulator for an area-efficient, reconfigurable, energy-efficient, speed-efficient neural network |
Dharmendra S. Modha |
2021-12-21 |
| 11200496 |
Hardware-software co-design of neurosynaptic systems |
John V. Arthur, Steven K. Esser, Myron D. Flickner, Dharmendra S. Modha, Tapan K. Nayak |
2021-12-14 |
| 11176446 |
Compositional prototypes for scalable neurosynaptic networks |
Arnon Amir, Dharmendra S. Modha, Benjamin G. Shaw |
2021-11-16 |
| 11157795 |
Graph partitioning and placement for multi-chip neurosynaptic networks |
Arnon Amir, Myron D. Flickner, Dharmendra S. Modha, Tapan K. Nayak |
2021-10-26 |
| 11010662 |
Massively parallel neural inference computing elements |
Rathinakumar Appuswamy, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner +5 more |
2021-05-18 |
| 10984312 |
Mapping graphs onto core-based neuromorphic architectures |
Arnon Amir, Paul A. Merolla, Dharmendra S. Modha |
2021-04-20 |
