Issued Patents 2021
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11200496 | Hardware-software co-design of neurosynaptic systems | Pallab Datta, Steven K. Esser, Myron D. Flickner, Dharmendra S. Modha, Tapan K. Nayak | 2021-12-14 |
| 11184221 | Yield tolerance in a neurosynaptic system | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-11-23 |
| 11074496 | Providing transposable access to a synapse array using a recursive array layout | John E. Barth, Jr., Paul A. Merolla, Dharmendra S. Modha | 2021-07-27 |
| 11049001 | Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural network | Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-06-29 |
| 11010662 | Massively parallel neural inference computing elements | Rathinakumar Appuswamy, Andrew S. Cassidy, Pallab Datta, Steven K. Esser, Myron D. Flickner +5 more | 2021-05-18 |
| 10990872 | Energy-efficient time-multiplexed neurosynaptic core for implementing neural networks spanning power- and area-efficiency | Filipp A. Akopyan, Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Steven K. Esser, Bryan L. Jackson +3 more | 2021-04-27 |
| 10984307 | Peripheral device interconnections for neurosynaptic systems | Filipp A. Akopyan, Rodrigo Alvarez-Icaza Rivera, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla +2 more | 2021-04-20 |
| 10929747 | Dual deterministic and stochastic neurosynaptic core circuit | Rodrigo Alvarez-Icaza, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha +1 more | 2021-02-23 |