Issued Patents 2020
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10818595 | Semiconductor structure, testing and fabricating methods thereof | Yen-Hsung Ho, Chia-Yi Tseng, Chih-Hsun Lin, Yung-Lung Hsu | 2020-10-27 |
| 10790391 | Source/drain epitaxial layer profile | Gulbagh Singh, Hsin-Chi Chen | 2020-09-29 |
| 10672777 | Method of manufacturing semiconductor device having multi-height structure | Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Chiang-Ming Chuang, Chia-Yi Tseng | 2020-06-02 |
| 10672795 | Bulk semiconductor substrate configured to exhibit semiconductor-on-insulator behavior | Gulbagh Singh, Hsin-Chi Chen | 2020-06-02 |
| 10636695 | Negatively sloped isolation structures | Gulbagh Singh, Tsung-Han Tsai | 2020-04-28 |
| 10636870 | Isolation regions for reduced junction leakage | Gulbagh Singh, Hsin-Chi Chen | 2020-04-28 |
| 10546937 | Structures and methods for noise isolation in semiconductor devices | Gulbagh Singh, Tsung-Han Tsai | 2020-01-28 |
| 10535670 | Non-volatile memory having an erase gate formed between two floating gates with two word lines formed on other sides and a method for forming the same | Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Hung-Che Liao, Chia-Ming Pan +1 more | 2020-01-14 |