Issued Patents 2020
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879257 | Integrated chip having a logic gate electrode and a tunnel dielectric layer | Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2020-12-29 |
| 10872777 | Self-aligned double patterning (SADP) method | Kuo-Chyuan Tzeng, Lee-Chuan Tseng, Ying Chen | 2020-12-22 |