| 10818331 |
Multi-chip module for MRAM devices with levels of dynamic redundancy registers |
Benjamin Louie |
2020-10-27 |
| 10803949 |
Master slave level shift latch for word line decoder memory architecture |
Susmita Karmakar, Benjamin Louie |
2020-10-13 |
| 10699761 |
Word line decoder memory architecture |
Susmita Karmakar, Benjamin Louie |
2020-06-30 |
| 10656994 |
Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques |
Benjamin Louie, Mourad El-Baraji, Lester Crudele |
2020-05-19 |
| 10628316 |
Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register |
Benjamin Louie, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman |
2020-04-21 |
| 10580482 |
Memory device comprising electrically floating body transistor |
Jin-Woo Han, Yuniarto Widjaja |
2020-03-03 |
| 10546625 |
Method of optimizing write voltage based on error buffer occupancy |
Benjamin Louie, Kuk-Hwan Kim, TaeJin Pyon |
2020-01-28 |
| 10546624 |
Multi-port random access memory |
Mourad El-Baraji, Lester Crudele, Benjamin Louie |
2020-01-28 |
| 10529439 |
On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects |
Benjamin Louie, Mourad El-Baraji, Lester Crudele |
2020-01-07 |