| 10839905 |
Content addressable memory device having electrically floating body transistor |
Jin-Woo Han, Yuniarto Widjaja |
2020-11-17 |
| 10818331 |
Multi-chip module for MRAM devices with levels of dynamic redundancy registers |
Neal Berger |
2020-10-27 |
| 10803949 |
Master slave level shift latch for word line decoder memory architecture |
Neal Berger, Susmita Karmakar |
2020-10-13 |
| 10797055 |
Memory cell comprising first and second transistors and methods of operating |
Yuniarto Widjaja, Jin-Woo Han |
2020-10-06 |
| 10783952 |
Systems and methods for reducing standby power in floating body memory devices |
Yuniarto Widjaja |
2020-09-22 |
| 10699761 |
Word line decoder memory architecture |
Neal Berger, Susmita Karmakar |
2020-06-30 |
| 10656994 |
Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques |
Neal Berger, Mourad El-Baraji, Lester Crudele |
2020-05-19 |
| 10629599 |
Memory device having electrically floating body transistor |
Yuniarto Widjaja, Jin-Woo Han |
2020-04-21 |
| 10628316 |
Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register |
Neal Berger, Mourad El-Baraji, Lester Crudele, Daniel L. Hillman |
2020-04-21 |
| 10546860 |
NAND string utilizing floating body memory cell |
Jin-Woo Han, Yuniarto Widjaja |
2020-01-28 |
| 10546625 |
Method of optimizing write voltage based on error buffer occupancy |
Neal Berger, Kuk-Hwan Kim, TaeJin Pyon |
2020-01-28 |
| 10546624 |
Multi-port random access memory |
Mourad El-Baraji, Neal Berger, Lester Crudele |
2020-01-28 |
| 10529439 |
On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects |
Neal Berger, Mourad El-Baraji, Lester Crudele |
2020-01-07 |